`include "defines.v"

module RAM_1W2R(
    input clk,
    
    input [`BUSLEN]inst_addr,
    input inst_ena,
    output [`INSTLEN]inst,

    // DATA PORT
    input ram_wr_en,
    input ram_rd_en,
    input [`BUSLEN]ram_wmask,    
    input [`BUSLEN]ram_addr,
    input [`BUSLEN]ram_wr_data,
    output reg [`BUSLEN]ram_rd_data
);

    // INST PORT

    wire[`BUSLEN] inst_2 = ram_read_helper(inst_ena,{3'b000,(inst_addr-`PC_START)>>3});

    assign inst = inst_addr[2] ? inst_2[63:32] : inst_2[31:0];

    // DATA PORT 
    assign ram_rd_data = ram_read_helper(ram_rd_en, {3'b000,(ram_addr-`PC_START)>>3});

    always @(posedge clk) begin
        ram_write_helper((ram_addr-`PC_START)>>3, ram_wr_data, ram_wmask, ram_wr_en);
    end

endmodule